1. Technical Field
This disclosure relates to semiconductor devices and more particularly, to a buffer layer disposed within a dielectric layer to allow improved control of dielectric thickness and planarity and a method of forming the buffer layer.
2. Description of the Related Art
Semiconductor wafers, such as those made of silicon, are used as a substrate for processing integrated circuit chips. As processing has improved over the years wafer diameters have increased to their current size of approximately 8 inches and greater. Wafers are generally sliced off from a large silicon crystal ingot and are generally circular in shape.
Decreasing feature size for integrated circuit chips has increased the criticality of the planarity of the wafer. Today, with sub-micron features becoming widespread, surface planarity is assuming new importance, since it offers a key to boosting performance. Process control for these ever decreasing feature sizes increasingly becomes more dependent on surface uniformity and planarity. Surface uniformity and planarity is difficult to control especially when a surface layer has been exposed to many processing steps. The processing steps, for example dry etching, wet etching, or chemical mechanical polishing (CMP), may partially consume the surface layer reducing the planarity and adding non-uniformities on the surface.
Chemical mechanical polishing (CMP) is a process for improving the surface planarity of a semiconductor wafer and involves the use of mechanical pad polishing systems usually with a silica-based slurry. CMP offers a practical approach to achieving the important advantage of global wafer planarity. However, CMP systems for global planarization have certain limitations. These limitations include low wafer throughput, polished surface non-uniformity and a problem related to polishing uniformity known as "edge exclusion".
Surface non-uniformity often has a negative effect on photolithographic masking. Non-uniformities are carried through sequential processing resulting in variations in dielectric layers and performance of components. Photolithographic images are distorted having undesired effects on electronic components formed on the semiconductor chip.
As shown in FIG. 1, during manufacturing of trench capacitors in a semiconductor chip 10, a pad stack 11 is formed on the surface of the substrate. The pad stack comprises sequential pad layers. A first pad dielectric layer 14 is formed on the substrate 16. The first pad layer is typically a pad oxide layer formed by thermal oxidation. A second pad layer 12 is formed over the pad oxide layer, which typically comprises nitride.
The pad oxide layer promotes adhesion and reduces stress between the pad nitride layer and the substrate.
Above the pad nitride layer is hard mask layer 18. The hard mask layer is typically patterned to serve as a mask for etching of deep trenches used to form trench capacitors. The hard mask layer comprises, for example, TEOS or boron-silicate glass (BSG).
The pad nitride layer 12 serves as a polish and/or an etch stop layer. As such, the pad stop layer 12 is subjected to polishing steps and etching steps during processing. Pad layer 12 frequently has a non-uniform thickness due to this prior processing. In order for this layer to be effective as a polish or etch stop layer, it must maintain a certain minimum safe thickness if it is to act as a polish stop, for example. The non-uniformities created in earlier polishing and etching steps potentially leave "low spots" which can be below the minimum required thickness of the stop layer.
Therefore, a need exists for a method and apparatus for creating a uniform thickness layer which has been exposed to prior processing steps.